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data sheet rev. 1. 00 / october 2013 zspm 1025a true digital pwm controller (single - phase , single - rail ) smart power management ics power and precision
for more information, contact zmdi via spm@zmdi.com . zspm1025a true digital pwm controller (single - phase, single - rail) ? 2013 zentrum mikroelektronik dresden ag rev . 1.00 october 24 , 2013. all rights reserved. the material c o ntained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is sub ject to changes without notice. brief description the zspm1025a is a flexible true - digital single - phase pwm controller optimally configured for use with the murata power solutions 25a power block oklp - x/25 in smart digital power solutions. the zspm10 2 5a integrates a digital control loop, opti mized for maximum flexibility and stability, as well as load step and steady - state performance. in addition, a rich set of protection and monitoring functions is provided. on - chip, non - volatile memory (nvm) and an i 2 c ? * interface facilitate configurat ion . the pc - based zmdis pink power designer? pro - vides a user - friendly and easy - to - use interface to the zspm1025a for communication, monitoring, and configuration of the protection and sequencing features. features ? programmable digital control loop ? advanced digital control techniques ? tru - sample technology ? ? state - law control ? (slc) ? sub - cycle response ? (scr) ? improved transient response and noise immunity ? protection features ? over - current protection ? over - voltage protection (vin, vout) ? under - voltage prote ction (vin, vout) ? overloaded startup ? restart and delay ? fuse - based nvm for improved reliability ? operation from a single 5v or 3.3v supply ? optional pmbus? address selection without external resistors * i 2 c? is a registered trademark of nxp. benefits ? fast time - to - market using off - the - shelf, o ptimal ly configured controller and power block ? fast configurability and design flexibility ? simplified design flow and high reliability via proven system design solution ? reduced component count through system level integration ? simplified monitoring for system power and thermal management ? higher energy efficiency across all output loading conditions available support ? evaluation kit ? pc - based pink power designer? physical characteristics ? operation temperature: - 40 c to + 12 5c ? v out max: 3.6 v ? lead free (rohs compli ant) 24 - pin qfn p ackage (4 mm x 4 mm) zspm10 25a typical application diagram driver zspm 1025 qfn 4 x 4 mm murata oklp - x / 25 - w 12 - c current sensing digital control loop power management ( sequencing , protection , ) housekeeping and communication driver
zspm1025a true digital pwm controller (single - phase, single - rail) ? 2013 zentrum mikroelektronik dresden ag rev. 1.00 october 24 , 2013. all rights reserved. the material c o ntained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. typical applications ? telecom switch es ? servers and storage ? base station s ? network routers ? industrial applications ? si ngle - rail/single - phase supplies for processors, asic s , fpga s , dsp s ordering informatio n sales code description package zspm10 25 aa1w 1 zspm10 25a lead - f ree qfn24 temperature range: - 40c to +125 c reel zspm80 25 - kit evaluation kit for zspm10 25a with pmbus? communication interface and pink power designer? gui kit sales and further information www.zmdi.com spm@zmdi.com zentrum mikroelektronik dresden ag global headquarters grenzstrasse 28 01109 dresden, germany central office: phone +49.351.8822.0 fax +49.351.8822.600 zmd america, inc. 1525 mccarthy blvd., #212 milpitas, ca 95035 - 7453 usa usa phone +855.275.9634 zentrum mikroelektronik dresden ag, japan office 2nd floor, shinbashi tokyu bldg. 4 - 21 - 3, shinbashi, minato - ku tokyo, 105 - 0004 japan zmd far east, ltd. 3f, no. 51, sec. 2, keelung road 11052 taipei taiwan zentrum mikroelektronik dresden ag, korea office u - space 1 building 11th floor, unit ja - 1102 670 sampyeong - do ng bundang - gu, seongnam - si gyeonggi - do, 463 - 400 korea phone +82.31.950.7679 fax +82.504.841.3026 phone +408.883.6310 fax +408.883.6358 phone +81.3.6895.7410 fax +81.3.6895.7301 phone +886.2.2377.8189 fax +886.2.2377.8199 european technical support phone +49.351.8822.7.772 fax +49.351.8822.87.772 disclaimer : this information applies to a product under development. its characteristics and specifications are subject to change witho ut notice. zentrum mikroelek tronik dresden ag (zmd ag) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. the information furnished hereby is believed to be true and accurate. however, under no circumstances shall zmd ag be liable to a ny customer, lic ensee, or any other third party for any special, indirect, incidental, or consequential damages of any kind or nature whatsoe ver arising out of or in any way related to the furnishing, performance, or use of this technical data. zmd ag hereby expressly dis claims any liability of zmd ag to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liab ility of zmd ag for any damages in connection with or arising out of the furnishing, performa nce or use of this technical data, whether based on contract, warranty, tort (including negligence), strict liability, or otherwise. european sales (stuttgart) phone +49.711.674517.55 fax +49.711.674517.87955 zspm10 25a block diagram sequencer configurable error handler clock generation ov detection oc detection flash adc cpu core nvm ( otp ) 1 . 8 v reg digital 1 . 8 v reg analog vref vfbp vfbn v d d 5 0 avdd 18 vdd 18 adaptive digital controller pwm lse pwm vfb digital control loop isnsp isnsn current sensing hkadc int . temp sense temp bias current source vrefp 3 . 3 v reg a d c v r e f smbus gpio g p i o 0 p g o o d c o n t r o l s d a s c l s m b a l e r t dac dac current limiting average current sensing ot detection vin ov / uv detection addr 0 addr 1 vin vdd 33 vout uv detection
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 4 of 46 contents list of figures ................................ ................................ ................................ ................................ .......................... 5 list of tables ................................ ................................ ................................ ................................ ........................... 7 1 ic characteristics ................................ ................................ ................................ ................................ ............. 8 1.1. absolute maximum ratings ................................ ................................ ................................ ....................... 8 1.2. recommended operat ing conditions ................................ ................................ ................................ ....... 9 1.3. electrical parameters ................................ ................................ ................................ ................................ 9 2 product summary ................................ ................................ ................................ ................................ ........... 12 2.1. overview ................................ ................................ ................................ ................................ .................. 12 2.2. pin description ................................ ................................ ................................ ................................ ......... 14 2.3. available packages ................................ ................................ ................................ ................................ . 15 3 functional description ................................ ................................ ................................ ................................ .... 16 3.1. power supply circuitry, reference decoupling, and grounding ................................ ............................ 16 3.2. reset/start - up behavior ................................ ................................ ................................ .......................... 16 3.3. digital power contro l ................................ ................................ ................................ ............................... 16 3.3.1. overview ................................ ................................ ................................ ................................ ........... 16 3.3.2. output voltage feedback ................................ ................................ ................................ ................. 16 3.3.3. digital compensator ................................ ................................ ................................ ......................... 17 3.3.4. power sequencing and the control pin ................................ ................................ ...................... 17 3.3.5. pre - biased start - up and soft stop ................................ ................................ ................................ .... 18 3.3.6. current sens ing ................................ ................................ ................................ ................................ 19 3.3.7. temperature measurement ................................ ................................ ................................ .............. 20 3.4. fault monitoring and response generation ................................ ................................ ............................ 20 3.4.1. output over/under - voltage ................................ ................................ ................................ .............. 21 3.4.2. output current protection and limiting ................................ ................................ ............................ 21 3.4.3. over - temperature protection ................................ ................................ ................................ ........... 21 3.5. configuration ................................ ................................ ................................ ................................ ........... 21 4 pmbus? functionality ................................ ................................ ................................ ................................ ... 22 4.1. introduction ................................ ................................ ................................ ................................ .............. 22 4.2. timing and bus specification ................................ ................................ ................................ .................. 22 4.3. address selection via external resistors ................................ ................................ ................................ 23 4.4. configuration registers ................................ ................................ ................................ ........................... 24 4.5. monitoring ................................ ................................ ................................ ................................ ................ 26 4.6. additional registers ................................ ................................ ................................ ................................ . 26 4.7. detailed description of the supported pmbus? commands ................................ ................................ . 27 4.7.1. operation ................................ ................................ ................................ ................................ ..... 27 4.7.2. on_off_config ................................ ................................ ................................ ............................ 27 4.7. 3. clear_faults ................................ ................................ ................................ .............................. 27 4.7.4. vout_mode ................................ ................................ ................................ ................................ ... 28 4.7.5. vout_command ................................ ................................ ................................ ........................... 28 4.7.6. status_byte ................................ ................................ ................................ ................................ . 28 4.7.7. status_word ................................ ................................ ................................ ............................... 29
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 5 of 46 4.7.8. status_vout ................................ ................................ ................................ ................................ 29 4.7.9. status_iout ................................ ................................ ................................ ................................ . 30 4.7.10. status_input ................................ ................................ ................................ ............................... 30 4.7.11. status_temperature ................................ ................................ ................................ ............... 30 4.7.12. status_cml ................................ ................................ ................................ ................................ .. 31 4.7.13. status_mfr_specific ................................ ................................ ................................ ............... 31 4.7.14. read_vin ................................ ................................ ................................ ................................ ........ 31 4.7.15. read_vout ................................ ................................ ................................ ................................ .... 31 4.7.16. read_iout ................................ ................................ ................................ ................................ ...... 32 4.7.17. read_temperature1 ................................ ................................ ................................ ................. 32 4.7.18. read_temperature2 ................................ ................................ ................................ ................. 32 5 application information ................................ ................................ ................................ ................................ ... 33 5.1. typical application circuit ................................ ................................ ................................ ....................... 33 5.1.1. output voltage selection ................................ ................................ ................................ .................. 35 5.1.2. output capacitor selection ................................ ................................ ................................ ............... 35 5.2. typical performance measurements for the zspm1025a ................................ ................................ ...... 35 5.2.1. typical load transient response C capacitor range #1 C vout range #1 ................................ . 36 5.2.2. typical load transient response C capacitor range #2 C vout range #1 ................................ . 37 5.2.3. typical load transie nt response C capacitor range #3 C vout range #1 ................................ . 38 5.2.4. typical load transient response C capacitor range #4 C vout range #1 ................................ . 39 5.2.5. typical load transient response C capacitor range #1 C vout range #2 ................................ . 40 5.2.6. typical load transient response C capacitor range #2 C vout range #2 ................................ . 41 5.2.7. typical load transient response C capacitor range #3 C vout range #2 ................................ . 42 5.2.8. typical load transient response C capacitor range #4 C vout range #2 ................................ . 43 6 mechanical specifications ................................ ................................ ................................ .............................. 44 7 ordering information ................................ ................................ ................................ ................................ ...... 45 8 related documents ................................ ................................ ................................ ................................ ........ 45 9 glossary ................................ ................................ ................................ ................................ ......................... 45 10 document revision history ................................ ................................ ................................ ............................ 46 list of figures figure 2.1 typical application circuit with a 5v supply voltage ................................ ................................ ....... 12 figure 2.2 block diagram ................................ ................................ ................................ ................................ ... 13 figure 2.3 pin - out qfn24 package ................................ ................................ ................................ ................... 1 5 figure 3.1 simplified block diagram of the digital compensation ................................ ................................ .... 17 figure 3.2 power sequencing ................................ ................................ ................................ ............................ 18 figure 3.3 power sequencing with non - zero off voltage ................................ ................................ ................. 18 figure 3.4 inductor current sensing using the dcr method ................................ ................................ ............ 19 figure 4.1 pmbus? timing diagram ................................ ................................ ................................ ................ 22 figure 5.1 application circuit with a 5v supply voltage ................................ ................................ .................... 33
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 6 of 46 figure 5.2 5 to 15a load step C min. capacitance ................................ ................................ ........................... 36 fi gure 5.3 15 to 5a load step C min. capacitance ................................ ................................ ........................... 36 figure 5.4 5 to 15a load step C max. capacitance ................................ ................................ .......................... 36 figure 5.5 15 to 5a load step C max. capacitance ................................ ................................ .......................... 36 figure 5.6 open loop bode plots ................................ ................................ ................................ ...................... 36 figure 5.7 5 to 15a load step C min. capacitance ................................ ................................ ........................... 37 figure 5.8 15 to 5a load step C min. capacitance ................................ ................................ ........................... 37 figure 5.9 5 to 15a load step C max. capacitance ................................ ................................ .......................... 37 figure 5.10 15 to 5a load step C min. capacitance ................................ ................................ ........................... 37 figure 5.11 open loop bode plots ................................ ................................ ................................ ...................... 37 figure 5.12 5 to 1 5a load step C min. capacitance ................................ ................................ ........................... 38 figure 5.13 15 to 5a load step C min. capacitance ................................ ................................ ........................... 38 figure 5.14 5 to 15a load step C max. capacitance ................................ ................................ .......................... 38 figure 5.15 15 to 5a load step C max. capacitance ................................ ................................ .......................... 38 fi gure 5.16 open loop bode plots ................................ ................................ ................................ ...................... 38 figure 5.17 5 to 15a load step C min. capacitance ................................ ................................ ........................... 39 figure 5.18 15 to 5a load step C min. capacitance ................................ ................................ ........................... 39 figure 5.19 5 to 15a load step C max. capacitance ................................ ................................ .......................... 39 fi gure 5.20 15 to 5a load step C max. capacitance ................................ ................................ .......................... 39 figure 5.21 open loop bode plots ................................ ................................ ................................ ...................... 39 figure 5.22 5 to 20a load step C min. capacitance ................................ ................................ ........................... 40 figure 5.23 20 to 5a load step C min. capacitance ................................ ................................ ........................... 40 figure 5.24 5 to 20a load step C max. capacitance ................................ ................................ .......................... 40 figure 5.25 20 to 5a load step C max. capacitance ................................ ................................ .......................... 40 fi gure 5.26 open loop bode plots ................................ ................................ ................................ ...................... 40 figure 5.27 5 to 20a load step C min. capacitance ................................ ................................ ........................... 41 figure 5.28 20 to 5a load step C min. capacitance ................................ ................................ ........................... 41 figure 5.29 5 to 20a load step C max. capacitance ................................ ................................ .......................... 41 figure 5.30 20 to 5a load step C max. capacitance ................................ ................................ .......................... 41 figure 5.31 open loop bode plots ................................ ................................ ................................ ...................... 41 figure 5.32 5 to 20a load step C min. capacitance ................................ ................................ ........................... 42 fi gure 5.33 20 to 5a load step C min. capacitance ................................ ................................ ........................... 42 figure 5.34 5 to 20a load step C max. capacitance ................................ ................................ .......................... 42 figure 5.35 20 to 5a load step C max. capacitance ................................ ................................ .......................... 42 figure 5.36 open loop bode plots ................................ ................................ ................................ ...................... 42 figure 5.37 5 to 20a load step C min. capacitance ................................ ................................ ........................... 43 fi gure 5.38 20 to 5a load step C min. capacitance ................................ ................................ ........................... 43 figure 5.39 5 to 20a load step C max. capacitance ................................ ................................ .......................... 43 figure 5.40 20 to 5a load step C max. capacitance ................................ ................................ .......................... 43 figure 5.41 open loop bode plots ................................ ................................ ................................ ...................... 43 figure 6.1 package dr awing ................................ ................................ ................................ .............................. 44
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 7 of 46 list of tables table 3.1 fault configuration overview ................................ ................................ ................................ ........... 20 table 4.1 pmbus? timing specification ................................ ................................ ................................ ......... 22 table 4.2 support ed resistor values for pmbus? address selection ................................ ........................... 23 table 4.3 pmbus? address selection without resistors ................................ ................................ ................ 24 table 4.4 list of supported pmbus? configuration registers ................................ ................................ ........ 24 table 4.5 list of supported pmbus? status registers ................................ ................................ ................... 26 table 4.6 additional supported pmbus? registers ................................ ................................ ........................ 26 tabl e 4.7 supported pmbus? operation modes ................................ ................................ ............................ 27 table 4.8 supported pmbus? on_off_config options ................................ ................................ ............ 27 table 5.1 passive component values for the application circuit ................................ ................................ .... 34 table 5.2 output voltage ranges ................................ ................................ ................................ .................... 35 table 5.3 recommended output capacitor ranges ................................ ................................ ........................ 35
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 8 of 46 1 ic c haracteristics note: the absolute maximum ratings are stress ratings only. the zspm1025a might not fu nction or be operable above the recommended operating conditions. stresses exceeding the absolute maximum ratings might also damage the device. in addition, extended exposure to stresses above the recommended operating conditions might affect device reliab ility. zmdi does not recommend designing to the absolute maximum ratings. 1.1. absolute maximum ratings parameter pins conditions min typ max units supply voltages 5 v supply voltage vdd50 dv/dt < 0.15v/ s - 0.3 5.5 v max imum slew rate 0.15 v/ s 3.3 v supply voltage vdd33 - 0.3 3.6 v 1.8 v supply voltage vdd18 avdd18 - 0.3 2.0 v digital pins digital i/o pins scl sd a smbalert gpio0 control pgood lse pwm - 0.3 5.5 v analog pins current sensing isnsp, isnsn - 0.3 5.5 v voltage feedback vfbp vfbn - 0.3 2.0 v all other analog pin s adc v ref vrefp temp vin addr0 addr1 - 0.3 2.0 v ambient conditions storage temperature t stor - 40 150 c
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 9 of 46 1.2. recommended operating conditions parameter symbol conditions min typ max units ambient o peration temperature t amb - 40 125 c thermal resistance junction to ambient ? ja 40 k/w 1.3. electrical parameters parameter symbol conditions min typ max units supply voltages 5 v supply voltage vdd50 pin v vdd50 4. 7 5 5 .0 5. 2 5 v 5 v supply current i vdd50 vdd50 =5.0 v 23 ma 3.3 v supply voltage v vdd33 supply for both the vdd33 and vdd50 pins if the internal 3.3v regulator is not used. 3.0 3.3 3.6 v 3.3 v supply current i vdd33 vdd50 = vdd33 =3.3 v 23 ma internally generated supply voltages 3.3 v supply volta ge vdd33 pin v vdd33 vdd50 =5.0 v 3.0 3.3 3.6 v 3.3 v output current i vdd33 vdd50=5.0 v 2.0 ma 1.8 v supply voltages avdd18 and vdd18 pins v avdd18 v vdd18 vdd50=5.0 v 1.72 1.80 1.98 v 1.8 v output current 0 ma power on reset (por) threshold for vdd33 pin C on v th_por_on 2.8 v power on reset threshold for vdd33 pin C off v th_por_off 2.6 v digital io pins (gpio0, control, pgood) input high voltage vdd33 =3.3 v 2.0 v input low voltage vdd33 =3.3 v 0.8 v output high voltage vdd33 =3.3 v 2.4 vdd33 v output low voltage 0. 5 v input leakage current 1 .0 a output current C high 2.0 ma output current C low 2.0 ma digital io pins with tri - state capability (lse, pwm) output high voltage vdd33=3.3 v 2.4 vdd33 v output low voltage 0.5 v
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 10 of 46 parameter symbol conditions min typ max units output current C high 2.0 ma output current C low 2.0 ma tri - state leakage current 1.0 a smbus pins (scl, sda, smbalert) C open drain input high voltage vdd33=3.3 v 2.0 v input low voltage vdd33=3.3 v 0.8 v maximum bus voltage 5.25 v output current C low 2.0 ma output voltage* set - point voltage 0 1.4 v set - point resolution 1.4 mv set - point accuracy vout= 1. 2 v 1 % *without external voltage divider (see section 3.3.2 ) inductor current measurement common mode voltage isnsp and isnsn pins relative to agnd 0 5.0 v differential voltage range across isnsp and isnsn pins 100 mv accuracy 5 % recommended dcr sense volt age for maximum output current 10 mv digital pulse width modulator switching frequency f sw 500 khz resolution 163 ps frequency accuracy 2.0 % over - voltage protection reference dac set - point voltage 0 1.58 v resolution 25 mv set point accuracy 2 % comparator hysteresis 35 mv
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 11 of 46 parameter symbol conditions min typ max units housekeeping analog - to - digital converter (hkadc) input pins input voltage temp, vin, addr0, and addr1 pins 0 1.44 v source impedance vin sensing 3 k ? adc resolution 0.7 mv external temperature measurement ** bias currents for external temperature sensing temp pin 60 a resolution temp pin 0. 16 k accuracy of measurement temp pin 5.0 k ** supported sense elements: pn - junction internal temperature measurement resolution 0.22 k accuracy of measurement 5.0 k
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 12 of 46 2 product summary 2.1. overview the zspm10 25a is a flexible true - digital single - phase pwm controller optimally configured for use with the murata power solutions 25a power block oklp - x/25 in smart digital power solutions . it offers a pmbus? - configurable digital power control loop , incorporating output voltage sensing and average inductor current sensing , bundled with extensive fa ult monitoring and handling options. s everal different functional units are integrated in the device . a dedicated digital control loop is used to provide fast loop response and optimal output voltage regulation. this includes output voltage sensing, averag e inductor current sensing, a digital control law , and a digital pulse - width modulator (dpwm). in parallel, a dedicated, configurable error handler allows for fast and flexible detection of error sign als and their appropriate handling . a housekeeping analo g - to - digital converter (hkadc) ensures the reliable and efficient measurement of environmental signals , such as input voltage and temperature. an application - specific, low - energy integrated microcontroller is use d to control the overall system. among other things, it manages configuration of the various logic unit s and handles the pmbus? communication protocol. a pmbus? /smbus/ i2c? interface is incorporated to connect with the outside world; supported by control and power - good signals. figure 2 . 1 typical application circuit with a 5v supply voltage control pgood gpio 0 smbalert sda scl addr 1 addr 0 agnd adcvref vrefp avdd 18 vdd 18 vdd 50 vdd 33 gnd vin temp pwm lse isnsp isnsn vfbp vfbn + 5 v + vout pgnd vin c 1 , c 2 , c 3 c 4 , c 5 , c 6 r 1 r 2 , r 3 r 4 c 8 r 7 r 8 r 5 r 6 c 7 pmbus ? interface zspm 1025 a murata oklp - x / 25 - w 12 - c vin + 5 v + 5 v gnd pwm temp vout + cs - cs gnd enable cin cout
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 13 of 46 a high - reliability, high - temperature one - time programmable memory (otp) is used to store configuration param - eters. all required bias and reference voltages are int ernally derived from the external supply voltage. figure 2 . 2 block d iagram sequencer configurable error handler clock generation ov detection oc detection flash adc cpu core nvm ( otp ) 1 . 8 v reg digital 1 . 8 v reg analog vref vfbp vfbn v d d 5 0 avdd 18 vdd 18 adaptive digital controller pwm lse pwm vfb digital control loop isnsp isnsn current sensing hkadc int . temp sense temp bias current source vrefp 3 . 3 v reg a d c v r e f smbus gpio g p i o 0 p g o o d c o n t r o l s d a s c l s m b a l e r t dac dac current limiting average current sensing ot detection vin ov / uv detection addr 0 addr 1 vin vdd 33 vout uv detection
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 14 of 46 2.2. pin descriptio n pin name direction type description 1 agnd input supply analog ground 2 vrefp output supply reference terminal 3 vfbp input analog positive input of d ifferential feedback voltage sensing 4 vfbn input analog negative input of d ifferential feedback voltage sensing 5 isnsp input analog positive input of d ifferential current sensing 6 isnsn input analog negative input of d ifferential current sensing 7 temp input analog connection to e xternal temperature sensing element 8 vin input analog power supply input voltage sensing 9 addr0 input analog smbus address selection 0 10 addr1 input analog smbus address selection 1 11 pwm output digital h igh - side fet c ontrol s ignal 12 lse output digital low - side fet control s ignal 13 pgood output digital pgood output (i nternal pull - down) 14 control input digital control input 15 gpio 0 input /output digital general purpose input/output pin 16 smbalert output pmbus? smbus alert output 17 sda input/output pmbus? smbus shift data i/o 18 scl input pmbus? smbus shift clock input (slave - only) 19 gnd input supply digital ground 20 vdd18 output supply internal 1.8 v digital supply terminal 21 vdd 33 input / output supply 3 .3 v supply voltage terminal 22 v dd 50 input supply 5.0 v supply voltage terminal 23 avdd18 output supply internal 1.8 v analog supply terminal 24 adcvref input analog analog - to - digital converter ( adc ) reference terminal pad pad input supply exposed pad, digital ground
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 15 of 46 2.3. available packages the zspm10 25a is available in a 24 - pin qfn package. the pin - out is shown in figure 2 . 3 . the mech a nical drawing of the package can be found in figure 6 . 1 . figure 2 . 3 pin - out qfn24 p ackage a d c v r e f a v d d 1 8 v d d 5 0 v d d 3 3 v d d 1 8 g n d pad 19 20 21 22 24 23 isnsp isnsn vfbp vfbn agnd 4 2 1 3 5 6 vrefp p w m l s e v i n t e m p a d d r 0 a d d r 1 7 8 12 10 9 11 control pgood smbalert sda scl 13 14 15 16 18 17 gpio 0
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 16 of 46 3 functional description 3.1. power s upply c ircuitry , r eference d ecoupling , and g rounding the zspm10 25a incorporate s several internal power regulators in order to derive all required supply and bias v oltage s from a single external supply v oltage . this supply v oltage can be either 5 v or 3.3 v depending on whether the internal 3.3 v regulator should be used. if the internal 3.3 v regulator is not used, 3.3 v must be supplied to the 3.3 and 5 v supply pin s . decoupling capacitors are required at the vdd33, vdd18, and avdd18 pins (1.0 f minimum; 4.7 f recommended). if the 5.0 v supply voltage is used, i.e. the internal 3.3 v regulator is used, a small load current can be drawn from the vdd33 pin . this can be used to supply pull - up resistors , for example. the reference v oltage s required for the analog - to - digital converters are generated within the zspm10 25a . e xternal decoupling must be provided betw een the vref p and adcvref pins . therefore, a 4 . 7 f capacitor is required at the vref p pin and a 100 n f capacitor is required at the adcvref pin . the two pins should be connected with ap proximately 50 ? resistance in order to provide sufficient decoupling between the pins . three different ground connections ( the pad, agnd pin, and gnd pin) are available on the outside of the pack - age. these should be connected together to a single ground tie. a differentiation between analog and digital ground is not required. 3.2. reset/ s tart - up b ehavior the zspm10 25a employs a n internal power - on - reset (por) circuit to ensure proper sta rt up and sh u t down with a changing supply voltage . o nce the supply voltage increases above the por threshold voltage , the zs pm1025a begins the internal start - up process. upon its completion , the device is ready for operation. 3.3. d igital power control 3.3.1. overview the digital power control loop consists of the integral parts required for the control functionality of the zspm10 25a . a high - speed analog fr ont - end is used to digitize the output volt age. a digital control core uses the acquired information to provide duty - cycle information to the pwm , which controls the drive signals to the power stage. 3.3.2. output voltage f eedback the v oltage feedback signal is sampled wit h a high - speed analog front - end. the feedback v oltage is differential ly measured and subtracted from the voltage reference provided by a reference digital - to - analog converter (dac) using an error amplifier. a flash adc is then used to convert th e v oltage into its digital equivalent. this is followed by i nternal digital filtering to improve the systems noise rejection. an external feedback divider is required for output voltages above 1.20v . t he reference dac generates a v oltage up to 1.44 v . k ee ping the v oltage on the feedback pin (vfbp) below 1.20 v guarantee s sufficient head room for the output voltage compensation loop .
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 17 of 46 3.3.3. digital compensator the sampled output v oltage is processed by a digital control loop in order to modulate the dpwm output signal s controlling the power stage. this digital control loop works as a v oltage - mode controller using a pid - type compensation. the basic structure of the controller is shown in figure 3 . 1 . the proprietary state - law ? control (slc) concept features two parallel compensators , steady - state operation, and fast transient operation. the zspm10 25a implements fast, reliable switching between the different compensation mode s in order to ensure good transient performance and quiet steady state. this allows tuning the compensators individually for the respect ive needs ; i.e. quiet steady - state and fast transient performance. figure 3 . 1 simplified block d iagram of the d igital c ompensation t hree additional techniques are used to improve transient performance further. ? tru - sample t echnology ? is used to acquire fast, accurate , and continuous information about the output voltage so that the device can react quickly to any change in output voltage. tru - sample te chnology? reduces phase - lag caused by sampling delays, reduces noise sensitivity , and improves transient performance. ? t h e sub - cycle response ? (scr) technique, a method to drive the dpwm asynchronous ly during load transients, allows limiting the maximum dev iation of the output voltage and recharging the output capacitors faster. ? a non - linear gain adjustment is used during large load transients to boost the loop gain and reduce the settling time. 3.3.4. power s equencing and the control p in the zspm10 25a supports pow er - sequencing features including programmable ramp up/down and delays. t he typical sequence of events is shown in figure 3 . 2 and follows the pmbus? standard. the individual values can be set using the ap propriate configuration setting , which can be selected using the pink power designer? gui . three different config uration options are supported to turn the device on. the device can be configured to turn on immediately after por, on a n operation_on command, or on an edge on the control pin. digital pid compensator steady - state transient coefficients non - linear gain operation mode detection digital error signal duty cycle
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 18 of 46 figure 3 . 2 power s equencing 3.3.5. pre - biased s tart - up and so ft stop dedicated pre - biased start - up logic ensures proper start - up of the power converter when the output capacitors are pre - charged to a non - zero output voltage . closed - loop stability is ensured during this phase. the zspm10 25a also supports pre - biased off, i.e. the output voltage is not ramped down to zero and instead remains at a predefined level (v off_nom ). this value can be configured via the pink power designer? . after receiving the shutdown command via the pmbus? or the co ntrol pin, the zspm10 25a ramps down the output voltage value to the predefined value. once the value is reached, the pwm output will be put into tri - state mode in order to put the output driver in to its tri - state mode. figure 3 . 3 power s equencing with n on - zero o ff voltage t t on _ delay t on _ rise t on _ max t off _ delay t off _ fall 0 v v outnom t off _ max operation _ on control pin operation _ off control pin t t on _ delay t on _ rise t on _ max t off _ delay t off _ fall 0 v v onnom t off _ max v offnom tri - state
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 19 of 46 3.3.6. current s ensing the zspm10 25a offers cycle - by - cycle average current sensing with configurabl e over - current protectio n . a dedicated adc is used to provide fast and accurate current information over the switch ing period. the acquired information is compared with configurable current thresholds to report warning and error levels to the user. dc r current sensing across the inductor and dedicated shunt resistor s are supported . ad ditionally, the device uses dcr temperature compensation via the external temperature - sens ing element. this increases the accuracy of the current sense method by counteracting the significant change of the dcr over temperature. t o acquire accurate current information, the selection of the current sensing circuit is of critical importance. the schematic of the required current sensing circuitry is shown in figure 3 . 4 for the widely used dcr current - sensing method , which uses the parasitic resistance of the inductor to acquire the current information. the principle is based on a matched time - constant between the inductor and the low - pass filter buil t from a 2.15k resistor mounted on the murata power block and c 8 . re sistor r 6 should be a precision 2.15k resistor in order to provide good dc voltage rejection , .i.e. reduce the influence of the output voltage level in the current measure - ment. figure 3 . 4 inductor c urrent s ensing using the dcr m ethod end - of - line calibration is supported so that the zspm10 25a can achieve improved accuracy over the full output current range. the full calibration method is detailed in the zspm10xx application note programming and calibration . this allows the user to correct mismatches between the nominal dcr value used to configu re the device and the actual dcr value in the application caused by effect s such as manufacturing variations. the calibration range is limited to +/ - 50% of the nominal dcr value . zspm 1025 + vout 2 . 15 kohm r 6 2 . 15 kohm isnsp isnsn c 8 220 nf l dcr murata oklp - x / 25 - w 12 - c + cs - cs
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 20 of 46 additionally, in order to improve the accuracy of the current measurement , w hich can be adversely affected by the temperature coefficient of the inductors dcr, the zspm10 25a features temperature compensation via external temperature sensing. therefore, the temperature of the inductors is measur ed with an external temperature - sens ing element placed close to the inductor. this information is used to adapt the gain of the current sense path to compensate for the increase in actual dcr. 3.3.7. temperature measurement the zspm10 25a features two independent temperature measurement units. t he i nternal temperature sensing measures the temperatures inside the zspm1025a. t he external temperature sens or is placed on the murata power block. the zspm1025a drives 60 a into the external temperature - sensing element and measures the voltage on the temp pin . the pink power designer? gui must be used to select the offset for configuration of the external temperature measurement. a temperature - offset calibration is highly recommended. 3.4. fault m onitoring and r esponse g ener ation the zspm10 25a monitors various signals during operation. depending o n the selected configuration, it can respond to events generate d by these signals. a wide range of options is configurable via the pink power designer? . t ypical monitoring within the zspm10 25a is a three - step process. first, an event is detected via a configurable set of thresholds. this e vent is then digitally filtered before the zspm10 25a react s with a defined response depending on the fault condition . for most monitored signals, a warning and a fault threshold can be configured. a warni ng typically sets a status flag (see section 4.7.6 ) but does not trigger a response ; whereas a fault also generates a response. the warning and fault events can be enabled for each parameter that the zspm1025 monitors (see table 3 . 1 ). the smb alert signal is asserted by the zspm1025a for any warning or fault that has been enabled. an overview of the faults that the zspm1025a can detect and the response to each fault is given in table 3 . 1 . table 3 . 1 fault configuration overview fault response type output over - voltage low impedance output under - voltage low - impedance input over - voltage off input under - voltage off over - current low - impedance external over - temperature off internal over - temperature off the zspm10 25a supports different response types depending on the fault detected. an off response ramps the output voltage down using the falling - edge sequencer setting s . the final state of the output signals depends on the value selected for v off _ nom . the l ow - impedance response clamps the pwm output to pgnd . the controller fault handling will infinitely try to restart the converter on a fault condition. in analog controllers, this infinite re - try feature is also known as hiccup mode.
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 21 of 46 3.4.1. output o ver / u nder - voltage to prevent damage to the load, the zspm10 25a utilizes an output over - v oltage protection circuit. t he v oltage at vfbp is continuously compared with a configurable fault threshold using a high - speed analog comparator. the fault threshold can be configured using the pink power designer? gui. if the v oltage exceeds the configured threshold, the fault response is generated and the pwm output is set to low impedance (clamped to pgnd ) . the v oltage fault level is generate d by a 6 - bit dac with a reference v oltage of 1.60 v resulting in 25 mv resolution . t he output v olt age is also sampled using the hkadc and continuously compared to a configurable output over - v oltage warning threshold . the warning threshold can be configured using the pink power designer? gui. if the output v oltage exceeds this threshold , a warning is generat ed. the zspm10 25a also mo nitors the output v oltage with two lower threshold s . if the output v oltage is below the under - v oltage warning level and above the under - v oltage fault level, an output v oltage under - v oltage warning is triggered. if the output v oltage falls below the fault level, a fault event is generat e d and the output is set to low impedance . 3.4.2. output c urrent p rotection and l imiting the zspm10 25a continuously monitors the average inductor current and utilizes this information to protect the power supp ly against excessive output current. the output over - current warning and fault threshold levels can be configured using the pink power designer? gui. if the fault level is exceeded, the pwm output is set to low impedance . 3.4.3. over - t emperature p rotection the zspm10 25a monitors internal and external temperature. for each, a warning and a fault level can be configured and an appropriate response can be enabled. 3.5. configuration the zspm10 25a incorporates two different sets of configuration parameters (see section 4.4 ) . the first set of configuration parameters can be configured during design time and can not be changed during run - time . the second set of configuration parameters can be configured during design time, but can also be reconfigured during run - time using the appropriate pmbus? command. note that these reconfigured values are not stored in the otp memory , so they are lost during power cycling the device. in order to evaluate the device and its configu ration on the bench, a special engineering mode is supported by the device and pink power designer? . in this engineering mode, the device can be reconfigured multiple times without writing the configuration into the otp. during this mode, the device starts up after power - on reset in an unconfigured state. the pink power designer? then provides the configuration to the zspm10 25a , enabling full operation without actually configuring the otp. the engineer can use this mode to evaluate the configuration on the bench. however, the configuration will be lost upon power - on - reset. after the design engineer has determined the final configuration options, an otp image can be created that is then written into the zspm10 25a . this can be either on the bench using the pin k power designer? or in end C of - line testing during mass production.
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 22 of 46 4 pmbus? functionality 4.1. introduction the zspm10 25a supports the pmbus? protocol to enable configuration, monitoring , and fault management during run - time . the pmbus? host controller is connected to the zspm10 25a via the pmbus? pins (sda and scl) . a dedicated smbalert pin is provided to notify the host that new status information is present. the zspm10 25a supports packet error correction (pec) according to the pmbus? specification. 4.2. timing and bus s pecification timing for the pmbus? signals is given in figure 4 . 1 . the pmbus? signal smbclk is the shift clock input on the scl pin on the zspm1025a (slave only) and the smbdat signal is the shift data input/output on the sda pin. figure 4 . 1 pmbus? t iming d iagram table 4 . 1 pmbus? t iming s pecification parameter symbol conditions min typ max units smbus operation frequency f smb 10 400 500 khz bus free time between start and stop t buf 1.3 s hold time after start condition t hd :sta 0.6 s repeat start condition setup time t su :sta 0.6 s stop condition setup time t su :sto 0.6 s data hold time t hd :dat 30 0 n s data setup time t su :dat 10 0 n s clock low time - out t timeout 25 35 s clock low period t low 1.3 s clock high period t high 0. 6 s cumulative clock low extend time t low :sext 25 m s clock or data fall time t f 300 n s clock or data rise time t r 300 n s s p t buf t hd : sta t low t r t hd : dat t high t f t su : dat s p t su : sto t su : sta smbclk smbdat
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 23 of 46 4.3. address selection via external resistor s pmbus? uses a 7 - bit device address to identify different devices connected to the bus. this address can be selected via external resistors connected to the addr x pins . the resistor values are sensed using the internal adc during the initialization phase and the appropriate pmbus? address is selected. note that the respective circuitry is only active during the initialization phase; hence no dc voltage can be measured at the pins. the supported pmbus? addresses and the value s of the respective required resistor s are listed in table 4 . 2 . table 4 . 2 support ed r esistor v alue s for pmbus? a ddress s election address (hex) addr1 addr0 address (hex) addr1 addr0 address (hex) addr1 addr0 address (hex) addr1 addr0 64 0 0 32 1.2 k 0 64 2.7 k 0 96 4.7 k 0 1 * 0 680 33 1.2 k 680 65 2.7 k 680 97 * 4.7 k 680 2 * 0 1.2 k 34 1.2 k 1.2 k 66 2.7 k 1.2 k 98 4.7 k 1.2 k 3 * 0 1.8 k 35 1.2 k 1.8 k 67 2.7 k 1.8 k 99 4.7 k 1.8 k 4 * 0 2.7 k 36 1.2 k 2.7 k 68 2.7 k 2.7 k 100 4.7 k 2.7 k 5 * 0 3.9 k 37 1.2 k 3.9 k 69 2.7 k 3.9 k 101 4.7 k 3.9 k 6 * 0 4.7 k 38 1.2 k 4.7 k 70 2.7 k 4.7 k 102 4.7 k 4.7 k 7 * 0 5.6 k 39 1.2 k 5.6 k 71 2.7 k 5.6 k 103 4.7 k 5.6 k 8 * 0 6.8 k 40 * 1.2 k 6.8 k 72 2.7 k 6.8 k 104 4.7 k 6.8 k 9 0 8.2 k 41 1.2 k 8.2 k 73 2.7 k 8.2 k 105 4.7 k 8.2 k 10 0 10 k 42 1.2 k 10 k 74 2.7 k 10 k 106 4.7 k 10 k 11 0 12 k 43 1.2 k 12 k 75 2.7 k 12 k 107 4.7 k 12 k 12 * 0 15 k 44 1.2 k 15 k 76 2.7 k 15 k 108 4.7 k 15 k 13 0 18 k 45 1.2 k 18 k 77 2.7 k 18 k 109 4.7 k 18 k 14 0 22 k 46 1.2 k 22 k 78 2.7 k 22 k 110 4.7 k 22 k 15 0 27 k 47 1.2 k 27 k 79 2.7 k 27 k 111 4.7 k 27 k 16 680 0 48 1.8 k 0 80 3.9 k 0 112 5.6 k 0 17 680 680 49 1.8 k 680 81 3.9 k 680 113 5.6 k 680 18 680 1.2 k 50 1.8 k 1.2 k 82 3.9 k 1.2 k 114 5.6 k 1.2 k 19 680 1.8 k 51 1.8 k 1.8 k 83 3.9 k 1.8 k 115 5.6 k 1.8 k 20 680 2.7 k 52 1.8 k 2.7 k 84 3.9 k 2.7 k 116 5.6 k 2.7 k 21 680 3.9 k 53 1.8 k 3.9 k 85 3.9 k 3.9 k 117 5.6 k 3.9 k 22 680 4.7 k 54 1.8 k 4.7 k 86 3.9 k 4.7 k 118 5.6 k 4.7 k 23 680 5.6 k 55 * 1.8 k 5.6 k 87 3.9 k 5.6 k 119 5.6 k 5.6 k 24 680 6.8 k 56 1.8 k 6.8 k 88 3.9 k 6.8 k 120 * 5.6 k 6.8 k 25 680 8.2 k 57 1.8 k 8.2 k 89 3.9 k 8.2 k 121 * 5.6 k 8.2 k 26 680 10 k 58 1.8 k 10 k 90 3.9 k 10 k 122 * 5.6 k 10 k 27 680 12 k 59 1.8 k 12 k 91 3.9 k 12 k 123 * 5.6 k 12 k 28 680 15 k 60 1.8 k 15 k 92 3.9 k 15 k 124 * 5.6 k 15 k 29 680 18 k 61 1.8 k 18 k 93 3.9 k 18 k 125 * 5.6 k 18 k 30 680 22 k 62 1.8 k 22 k 94 3.9 k 22 k 126 * 5.6 k 22 k 31 680 27 k 63 1.8 k 27 k 95 3.9 k 27 k 127 * 5.6 k 27 k note: the addresses marked with an asterisk (*) are reserv e d by the smbus specification.
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 24 of 46 if only four devices are used in a system, their respective addresses can alternatively be configured without resistors by connecting the pins to gnd or the avd d 18 pin . the pmbus? addresses selectable in this fashion are listed in table 4 . 3 . table 4 . 3 pmbus? a ddress s election without r esistors address addr1 addr0 15 gnd avdd18 48 avdd18 gnd 63 avdd18 avdd18 64 gnd gnd 4.4. configuration registers two different sets of configuration parameters are supported by the zspm10 25a . the first set of parameters can only be configured during the configuration phase of the zspm10 25a . these values are writ ten into the otp memory and can not be changed using pmbus? commands during run - time. a second set of parameters can also be configured during run - time using the appropriate pmbus? commands. the two groups are classified in the pmbus? configuration table ( table 4 . 4 ) . table 4 . 4 list of s upported pmbus? c onfiguration r egisters note: see i mportant notes at the end of the table. pmbus? p arameter description data f ormat classification output voltage on_off_config on/ off configuration n/a pmbus? vout_mode exponent of the vout_command value n/a read only vout_command set output v oltage linear ( 1 ) pmbus? vout_ov_fault_limit over - v oltage fault limit n/a otp vo ut_ov_warn_limit over - v oltage warning level n/a otp vout_uv_warn_limit under - v oltage warning level n/a otp vout_uv_fault_limit under - v oltage fault level n/a otp ou tput c urrent iout_oc_fault_limit over - current fault limit n/a otp iout_oc_warn_limit over - current warning level n/a otp te mperature - e xternal ot_fault_limit external o ver - temperature fault level n/a otp ot _warn_limit external o ver - temperature warning level n/a otp
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 25 of 46 pmbus? p arameter description data f ormat classification temperature - i nternal i ot_fault_limit internal o ver - temperature fault level n/a otp i o t_warn_limit internal o ver - temperature warning level n/a otp in put voltage vin_ov_fault_limit over - v oltage fault limit n/a otp vi n_ov_warn_limit over - v oltage warning level n/a otp vin_uv_warn_limit under - v oltage warning level n/a otp vin_uv_fault_limit under - v oltage fault level n/a otp st art - up behavior / p ower s equencing power_good_on power good on threshold n/a otp power_good_off power good off threshold n/a otp output voltage s equencing ton_delay turn - on delay n/a otp ton_rise turn - on rise time n/a otp ton_fault_max turn - on maximum fault time n/a otp toff_delay turn - off delay n/a otp toff_fall turn - off fall time n/a otp toff_warn_max turn - off maximum warning time n/a otp voff_nom soft - stop off value n/a otp notes: 1. vout_mode is read - only for this device. the zspm10 25a supports the linear data format according to the pmbus? specification. note that in accordance with the pmbus? specification, all commands related to the output voltage are subject to the vout_mode settings . note t hat vout_mode is read - only for the zspm10 25a .
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 26 of 46 4.5. monitoring the zspm10 25a has a dedicated set of pmbus? registers to enable advanced power management using extensive monitoring features. different warning and error flags can be read by the pmbus? master to ensure proper operation of the power converter or monitor the converters over the product lifetime . table 4 . 5 list of s upported pmbus? s tatus r egisters pmbus? command descri ption data f ormat clear_faults clear status information status_byte unit status byte status_word unit status word status_vout output v oltage status status_iout output current status status_input input status status_temperature temperature status status_cml communication and memory status read_vin input v oltage read back linear read_vout output v oltage read back linear read_iout output current read back linear read_temperature_1 external t emperature read back linear read_temperature_2 internal t emperature read back linear 4.6. additional registers table 4 . 6 additional s upported pmbus? r egisters pmbus? command description data l ength ( b yte) values pmbus _revision pmbus? revision 1 11 hex mfr_id manufacturer id 4 zmdi (5a hex , 4d hex , 44 hex , 49 hex ) mfr_model manufacturer model identifier 4 10 25 ( 31 hex , 30 hex , 30 hex , 30 hex ) mfr_revision manufacturer product revision 4 mfr_serial s erial number 12
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 27 of 46 4.7. detailed description of the supported pmbus? commands 4.7.1. operation the operation command is used to turn the unit on and off in conjunction with the input from the control pin. the unit stays in the commanded operating mode until a subsequent operation comman d or change in the state of the control pin instructs the device to change to another mode. the supported operation modes are listed in tabl e 4 . 7 . tabl e 4 . 7 supported pmbus? operation modes operation (read/write) bits[7:6] bits[5:4] bits[3:2] bits[1:0] unit on or off margin state 01 xx xx xx soft off (with sequencing) n/a 10 00 xx xx on off 4.7.2. on_off_config the on_off_config command is used to configure the combination of the control pin and the pmbus ? operation command that turn s the unit on or off. the supported configuration options are listed in table 4 . 8 . table 4 . 8 supported pmbus? on_off_config o ptions on_off_config (read/write) bits name description [0] control off value ignored. device always uses the programmed turn off delay and fall time . [1] control polarity 0: active low ( p ull pin low to start the unit) . 1: active high ( p ull pin high to start the unit) . [2] control e nable 0: unit ignores the control pin . 1: unit requires the contr ol pin to be asserted to start the unit.* [3] operation e nable 0: unit ignores the on/off settings in the operation command . 1: unit requires the on/off settings in the operation command to start the unit* . *depending on the configuration , both conditions must be in the on state in order to turn on the unit. 4.7.3. clear_faults the clear_faults command is used to clear any fault bits that have been set in the status registers. additionally, the smbalert signal is clear ed if it was previously asser ted. note that the device resumes opera - tion with the currently configured state after a clear_faults command has been issued . if a fault/warning is still present , the respective bit is set immediately again.
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 28 of 46 4.7.4. vout_mode the vout_mode command is used to retrieve information about the data format for all output voltage related commands. note that this is a read - only value. vout_mode (r ead only) bits name description [4:0] parameter 2s complement of the exponent [7:5] mode 000: linear data format 4.7.5. vout_command the vout_command is used to set the output voltage during run - time. note that the maximum output voltage is 3.6v. vout_ command (r ead /wr ite ) bits name description [15:0] mantiss a unsigned mantissa of output voltage in v. exponent can be retrieved via vout_mode command. 4.7.6. status_byte the status_byte command returns a summary of the most critical faults in one byte. status_byte (r ea d only) bits name description [0] none of the above a fault not listed in bits [7:1] has occurred. [1] cml a communication fault as occurred. [2] temperature a temperature fault or warning has occurred. [3] vin_uv an input under - voltage fault has occurred. [4] iout_oc an output over - current fault has occurred. [5] vout_ov an output over - voltage fault has occurred. [6] off this bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being enabled. [7] busy not supported.
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 29 of 46 4.7.7. status_word the status_word command return s a summary of the device status information in two data bytes. status_word (r ea d only) bits name description [ 7: 0] status_byte see status byte (section 4.7.6 ). [ 8 ] unknown not supported [9 ] other not supported [10 ] fans no supported [11 ] power_good# the power_good signal, if present, is negated. [12 ] mfr a manufacturer specific fault or warning has occurred. [13 ] input a n input related warning or fault has occurred. [14] iout/pout a n output current or output power warning or fault has occurred. [15] vout an output voltage related warning or fault has occurred. 4.7.8. status_vout status_vout (r ea d only) bits name description [0] not supported. [1] not supported. [2] not supported. [3] not supported. [4] vout_uv_flt an output voltage under - voltage fault has occurred. [5] vout_uv_warn an output voltage under - voltage warning has occurred. [6] vout_ov_warn an output voltage over - voltage warning has occurred. [7] vout_ov _flt an output voltage over - voltage fault has occurred.
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 30 of 46 4.7.9. status_iout status_i out (r ea d only) bits name description [0] not supported. [1] not supported. [2] not supported. [3] not supported. [4] not supported. [5] iout_oc_warn an over - current warning has occurred. [6] . n ot supported . [7] iout_oc_flt an over - current fault has occurred. 4.7.10. status_input status_input (r ea d only) bits name description [0] not supported. [1] not supported. [2] not supported. [3] not supported. [4] vin_uv_flt an input voltage under - voltage fault has occurred. [5] vin_uv_warn an input voltage under - voltage warning has occurred. [6] vin_ov_warn an input voltage over - voltage warning has occurred. [7] vin_ov_flt an input voltage over - voltage fault has occurred. 4.7.11. status_temperature status_temperature (r ea d only) bits name description [0] not supported. [1] not supported. [2] not supported. [3] not supported. [4] not supported. [5] not supported. [6] temp_ov_warn an (external) over - temperature warning has occurred. [7] temp_ov_flt an (external) over - temperature fault has occurred.
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 31 of 46 4.7.12. status_cml status_cml (r ea d only) bits name description [0] not supported. [1] smbus_flt smbus ? timeout or a format error has occurred. [2] not supported. [3] not supported. [4] not supported. [5] pec_flt a packet error check fault has occurred. [6] not supported. [7] cmd_flt an invalid or an unsupported command has been received. 4.7.13. status_ mfr_specific status_mfr_specific (r ea d only) bits name description [0] not supported. [1] not supported. [2] not supported. [3] not supported. [4] not supported. [5] not supported. [6] itemp_ov_warn an (in ternal) over - temperature warning has occurred. [7] itemp_ov_flt an ( in ternal) over - temperature fault has occurred. 4.7.14. read_vin read_vin (r ea d only) bits name description [15:0] vin input voltage in v (linear data format). 4.7.15. read_vout read_vout (r ea d only) bits name description [15:0] vout output voltage in v (linear data format). note that this command is mantissa only.
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 32 of 46 4.7.16. read_iout read_iout (r ea d only) bits name description [15:0] iout output current in a (linear data format). 4.7.17. read_temperature1 read_temperature1 (r ea d only) bits name description [15:0] temp1 external temperature in c (linear data format). 4.7.18. read_temperature2 read_temperature2 (r ea d only) bits name description [15:0] temp2 internal temperature in c (linear data format).
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 33 of 46 5 application information the zspm1025a has been designed and pre - configured to operate with the murata oklp - x/25 - w12 - c power block, which is a complete point - of - load solution for 25a output currents. this section includes information about the typical application circuit and recommended component values. zmdi provides zspm1025a configuration data that is do wnloadable from zmdi website as part of the pink power designer ? gui. while the solution is pre - configured, the design engineer has the flexibility to configure the output voltage and select one of the four pre - defined and common output capacitor ranges. included in the pink power designer? software is a wizard dialog for guiding the user through the design process step - by - step, which makes it a ready - made , easy and tested solution. 5.1. typical application c ircuit a schematic for the typical application circuit is shown in figure 5 . 1 . a list of recommended component values for the passive components can be found in table 5 . 1 . figure 5 . 1 application circuit with a 5v supply voltage notes: * pmbus ? scl and sda pull - up resistors r9/r10 can be tied to 3.3v or 5v d epending on the pmbus ? master controller. ** the on/off input can be active high or active low depending on the configuration of the control pin on the zspm1025a. smbalert sda scl addr 1 addr 0 agnd adcvref vrefp avdd 18 vdd 18 vdd 50 vdd 33 gnd vin temp pwm lse isnsp isnsn vfbp vfbn + 5 v + vout pgnd vin c 1 , c 2 , c 3 c 4 , c 5 , c 6 r 1 r 2 , r 3 r 4 c 8 r 7 r 8 r 5 r 6 c 7 pmbus ? interface zspm 1025 a murata oklp - x / 25 - w 12 - c vin + 5 v + 5 v gnd pwm temp vout + cs - cs gnd enable cin cout control pgood gpio 0 r 9 , r 10 + 3 . 3 / 5 v * on / off ** pgood
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 34 of 46 table 5 . 1 passive component v alues for the application circuit reference designator component v alue description c1 1 . 0 f ceramic capacitor . c2 4.7 f ceramic capacitor. recommended 4.7 f, minimum 1.0 f . c3 4.7 f ceramic capacitor. recommended 4.7 f, minimum 1.0 f . c4 4.7 f ceramic capacitor. recommended 4.7 f, minimum 1.0 f . c5 4.7 f ceramic capacitor. recommended 4.7 f, minimum 1.0 f . c6 100nf c7 22pf output voltage sense filtering capacitor. recommended 22pf, m aximum 1 nf . c8 220nf * dcr current - sense filter capacitor . cin input filter capacitors. can be a combination of ceramic and electrolytic capacitors. cout output filter capacitors. see section 5.1.2 for more information on the output capa citor selection. r1 51 * r2 , r3 select pmbus ? address resistor value from table 4 . 2 . r4 1.0k * output voltage divider bottom resistor. connect between the vfbp and vfbn pins. select r4 for the output voltage range from 1.2v to 3.6v . r5 1.7 4 k * output voltage divider top re sistor. connect between the output terminal and the vfbp pin. r6 2.15k * dcr current sense filter resistor . r7 9.1k * input voltage divider top resistor. connect between the main power input and the vin pin of the zspm1025a . r8 1.0k * input voltage divider bottom resistor. connect between the vin and agnd pin s of the zspm1025a. r9, r10 15k * pmbus ? scl and sda line pull - up resistors. the pull - up resistors can be tied to 3.3v or 5v depending on the supply voltage of the pmbus ? master. notes: * fixed component values that must not be changed .
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 35 of 46 5.1.1. output v oltage s election the zspm1025a can be configured to operate within two output voltage ranges (see table 5 . 2 ). if the required output voltage is within range #1 resistor r4 should not be placed on the application board. for output voltages within range #2 , resistor r4 should be placed on the applica tion board. table 5 . 2 output voltage ranges output voltage range minimum vout maximum vout #1 0.35v 1.20v #2 1.20v 3.60v 5.1.2. output capacitor selection the zspm1025a digital pwm controller can be configured to operate over a wide range of output capacitance. four ranges of output capacitance have been specified to match typical customer requirements (see table 5 . 3 ). typical performance measurements for both load trans ient performance and open - loop b ode plots can be found in section 5.2 . using less output capacitance than the minimum capacitance given in table 5 . 3 is not recom - mended . table 5 . 3 recommended output capacitor ranges capacitor range ceramic capacitor bulk electrolytic capacitors #1 minimum 200 f maximum 400 f none #2 minimum 400 f maximum 1000 f none #3 minimum 100 f maximum 600 f minimum 2 x 470 f, 7m esr maximum 5 x 470 f, 7m esr #4 minimum 400 f maximum 1000 f minimum 4 x 470 f, 7m esr maximum 10 x 470 f, 7m esr 5.2. typical performance measurements for the zspm1025a zmdi has designed eight set s of compensation loop parameters for the zspm1025 a . the compensation loop parameters have been designed for each of the two output - voltage ranges (see table 5 . 2 ) in combination with one of the four ranges of output capacitors (see table 5 . 3 ) . the pink power designer ? gui wizard can guide the user through a selection process and load the correct set of parameters for the selected output voltage and output capacitor range. please see the pink power designer ? gui user guide for more information on the wizard . load transient performance measurements and open loop bode plots for the eight configurations can be found in sections 5.2.1 to 5.2.8 . the transient load steps have been generated with a load resistor and a power mosfet located on the same circuit board as the zspm1025a and the mur ata oklp - x/25 - w12 - c power block. the zspm8025 evaluation k it can be used to further evaluate the performance of the zspm1025a for the four capacitor ranges.
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 36 of 46 5.2.1. typical load transient r esponse C capacitor range #1 C vout range #1 test conditions: v in = 12.0v, v out = 1.20v minimum output capacitance: 2 x 100 f/6.3v x5r maximum output capacitance: 3 x 100 f/6.3v x5r + 2 x 47 f /10v x7 r figure 5 . 2 5 to 15a load step C min . capacitance figure 5 . 3 15 to 5a load step C m in. capacitance figure 5 . 4 5 to 15a load step C max. capacitance figure 5 . 5 15 to 5a load step C max. capacitance figure 5 . 6 open loop bode plots -180 -150 -120 -90 -60 -30 0 -40 -30 -20 -10 0 10 20 30 40 1 10 100 phase [degrees] gain [db] frequency [khz] max caps - gain min caps - gain max caps - phase min caps - phase ch1 (blue): vout 10 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div ch1 (blue): vout 100mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div ch1 (blue): vout 100mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div ch1 (blue): vout 100mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 37 of 46 5.2.2. typical load transient response C capacitor range #2 C vout range #1 test conditions: v in = 12.0v, v out = 1.20v minimum output capacitance: 3 x 100 f/6.3v x5r + 2 x 47 f/10v x7r maximum output capacitance: 7 x 100 f/6.3v x5r + 4 x 47 f/10v x7 r figure 5 . 7 5 to 15a load step C min. capacitance figure 5 . 8 15 to 5a load step C min. capacitance figure 5 . 9 5 to 15a load step C max. capacitance figure 5 . 10 15 to 5a load step C min. capacitance figure 5 . 11 open loop bode plots -180 -150 -120 -90 -60 -30 0 -40 -30 -20 -10 0 10 20 30 40 1 10 100 phase [degrees] gain [db] frequency [khz] max caps - gain min caps - gain max caps - phase min caps - phase ch1 (blue): vout 5 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div ch1 (blue): vout 5 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div ch1 (blue): vout 5 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div ch1 (blue): vout 50 mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 38 of 46 5.2.3. typical load transient response C capacitor range #3 C vout range #1 test conditions: v in = 12.0v, v out = 1.20v minimum output capacitance: 1 x 100 f/6.3v x5r + 2 x 470 f/6.3v/7m aluminum electrolytic capacitor maximum output capacitance: 6 x 100 f/6.3v x5r + 5 x 470 f/6.3v/7m aluminum electrolytic capacitor figure 5 . 12 5 to 15a load step C min. capacitance figure 5 . 13 15 to 5a load step C min. capacitance figure 5 . 14 5 to 15a load step C max. capacitance figure 5 . 15 15 to 5a load step C max. capacitance figure 5 . 16 open loop bode plots -180 -150 -120 -90 -60 -30 0 -40 -30 -20 -10 0 10 20 30 40 1 10 100 phase [degrees] gain [db] frequency [khz] max caps - gain min caps - gain max caps - phase min caps - phase ch1 (blue): vout 2 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 20 s/div ch1 (blue): vout 2 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc tim e scale: 20 s/div ch1 (blue): vout 20 mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 20 s/div ch1 (blue): vout 2 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 20 s/div
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 39 of 46 5.2.4. typical load transient response C capacitor range # 4 C vout range #1 test conditions: v in = 12.0v, v out = 1.20v minimum output capacitance: 3 x 100 f/6.3v x5r + 2 x 47 f/10v x7r + 4 x 470 f/6.3v/7m aluminum electrolytic capacitor maximum output capacitance: 7 x 100 f/6.3v x5r + 4 x 47 f/10v x7r + 10 x 470 f/6.3v/7m aluminum electrolytic capacitor figure 5 . 17 5 to 15a load step C min. capa citance figure 5 . 18 15 to 5a load step C min. capacitance figure 5 . 19 5 to 15a load step C max. capacitance figure 5 . 20 15 to 5a load step C max. capacitance figure 5 . 21 open loop bode plots -180 -150 -120 -90 -60 -30 0 -40 -30 -20 -10 0 10 20 30 40 1 10 100 phase [degrees] gain [db] frequency [khz] max caps - gain min caps - gain max caps - phase min caps - phase ch1 (blue): vout 2 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 20 s/div ch1 (blue): vout 2 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 20 s/div ch1 (blue): vout 2 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 20 s/div ch1 (blue): vout 2 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 20 s/div
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 40 of 46 5.2.5. typical load transient response C capacitor range # 1 C vout range #2 test conditions: v in = 12.0v, v out = 1.80v minimum output capacitance: 2 x 100 f/6.3v x5r maximum output capacitance: 3 x 100 f/6.3v x5r + 2 x 47 f/10v x7r figure 5 . 22 5 to 20 a load step C min. capacitance figure 5 . 23 20 to 5a load step C min. capacitance figure 5 . 24 5 to 20 a load step C max. capacitance figure 5 . 25 20 to 5a load step C max. capacitance figure 5 . 26 open loop bode plots -180 -150 -120 -90 -60 -30 0 -40 -30 -20 -10 0 10 20 30 40 1 10 100 phase [degrees] gain [db] frequency [khz] max caps - gain min caps - gain max caps - phase min caps - phase ch1 (blue): vout 100 mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div ch1 (blue): vout 100mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div ch1 (blue): vout 100mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div ch1 (blue): vout 100mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc tim e scale: 8 s/div
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 41 of 46 5.2.6. typical load transient response C capacitor range #2 C vout range #2 test conditions: v in = 12.0v, v out = 1.80v minimum output capacitance: 3 x 100 f/6.3v x5r + 2 x 47 f/10v x7r maximum output capacitance: 7 x 100 f/6.3v x5r + 4 x 47 f/10v x7r figure 5 . 27 5 to 20 a load step C min. capacitance figure 5 . 28 20 to 5a load step C min. capacitance figure 5 . 29 5 to 20 a load step C max. capacitance figure 5 . 30 20 to 5a load step C max. capacitance figure 5 . 31 open loop bode plots -180 -150 -120 -90 -60 -30 0 -40 -30 -20 -10 0 10 20 30 40 1 10 100 phase [degrees] gain [db] frequency [khz] max caps - gain min caps - gain max caps - phase min caps - phase ch1 (blue): vout 5 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div ch1 (blue): vout 5 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div ch1 (blue): vout 50 mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div ch1 (blue): vout 5 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 42 of 46 5.2.7. typical load transient response C capacitor range # 3 C vout range #2 test conditions: v in = 12.0v, v out = 1.80v minimum output capacitance: 1 x 100 f/6.3v x5r + 2 x 470 f/6.3v/7m aluminum electrolytic capacitor maximum output capacitance: 6 x 100 f/6.3v x5r + 5 x 470 f/6.3v/7m aluminum electrolytic capacitor figure 5 . 32 5 to 20 a load step C min. capacitance figure 5 . 33 20 to 5a load step C min. capacitance figure 5 . 34 5 to 20 a load step C max. capacitance figure 5 . 35 20 to 5a load step C max. capacitance figure 5 . 36 open loop bode plots -180 -150 -120 -90 -60 -30 0 -40 -30 -20 -10 0 10 20 30 40 1 10 100 phase [degrees] gain [db] frequency [khz] max caps - gain min caps - gain max caps - phase min caps - phase ch1 (blue): vout 50mv/div ac ch2 (lcyan ): pwm 5v/div dc ch3: (violet): load trigger 5v/div dc time scale: 20 s/div ch1 (blue): vout 50mv/div ac ch2 (lcyan ): pwm 5v/div dc ch3: (violet): load trigger 5v/div dc time scale: 20 s/div ch1 (blue): vout 50mv/div ac ch2 ( lcyan ): pwm 5v/div dc ch3: (violet): load trigger 5v/div dc time scale: 20 s/div ch1 (blue): vout 50mv/div ac ch2 (lcyan ): pwm 5v/div dc ch3: (violet): load trigger 5v/div dc time scale: 20 s/div
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 43 of 46 5.2.8. typical load transient response C capacitor range # 4 C vout range #2 test conditions: v in = 12.0v, v out = 1.80v minimum output capacitance: 3 x 100 f/6.3v x5r + 2 x 47 f/10v x7r + 4 x 470 f/6.3v/7m aluminum electrolytic capacitor maximum output capacitance: 7 x 100 f/6.3v x5r + 4 x 47 f/10v x7r + 10 x 470 f/6.3v/7m aluminum electrolytic capacitor figu re 5 . 37 5 to 20 a load step C min. capacitance figure 5 . 38 20 to 5a load step C min. capacitance figure 5 . 39 5 to 20 a load step C max. capacitance figure 5 . 40 20 to 5a load step C max. capacitance figure 5 . 41 open loop bode plots -180 -150 -120 -90 -60 -30 0 -40 -30 -20 -10 0 10 20 30 40 1 10 100 phase [degrees] gain [db] frequency [khz] max caps - gain min caps - gain max caps - phase min caps - phase ch1 (blue): vout 2 0mv/div ac ch2 (lcyan ): pwm 5v/div dc ch3: (violet): load trigger 5v/div dc time scale: 20 s/div ch1 (blue): vout 20mv/div ac ch2 (lcyan ): pwm 5v/div dc ch3: (violet): load trigger 5v/div dc time scale: 20 s/div ch1 (blue): vout 20mv/div ac ch2 (lcyan ): pwm 5v/div dc ch3: (violet): load trigger 5v/div dc time scale: 20 s/div ch1 (blue): vout 20mv/div ac ch2 (lcyan ): pwm 5v/div dc ch3: (violet): load trigger 5v/div dc time scale: 20 s/div
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 44 of 46 6 mechanical specifications based on jedec mo - 220. all dimensions are in m illimeters. figure 6 . 1 package drawing dimensions [mm] m in m ax a 0.8 0.90 a 1 0.00 0.05 b 0.18 0.30 e 0.5 nom inal h d 3.90 4.1 h e 3.90 4.1 l 0.35 0.45
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 45 of 46 7 ordering information sales code description package zspm10 25 aa1w 1 zspm10 25a lead - f ree qfn24 temperature range: - 40 c to + 12 5c reel z spm80 25 - kit evaluation kit for zspm10 25 a : pmbus ? communication interface and pink power designer? gui kit 8 related documents note: x_xy refers to the current revision of the document. document file name zspm8025 a feature sheet zspm1025a_ feature _sheet _rev_x_xy.pdf zspm80 25 - kit evaluation kit description zspm80 25 _eval_kit_rev_x_xy.pdf pink power designer? graphic user interface (gui) userguide_rev_x_xy.pd f zspm10xx application note programming and calibration zspm10xx_calibration_procedures _revx_xx.pdf visit the zspm1025 product page ( www.zmdi.com/zspm1025 ) on zmdis website www.zmdi.com or contact your nearest sales office for the latest version of these documents. 9 glossary term description asic application specific integrated circuit dpwm digital pulse - width modulator dcr dc resistance dsp digital signal processing fpga field - programmable gate array gpio general purpose input/output gui graphical user interface hkadc housekeeping analog - to - digital converter nvm non - volatile memory ot over - temperature otp one - time programmable memory ov over - voltage pec p acket e rror c orrection pid proportional/integral/derivative scr sub - cycle response? slc state - law control ? spm smart power management
zspm1025a true digital pwm controller (single - phase, single - rail) data sheet october 2 4 , 2013 ? 2013 zentrum mikroelektronik dresden ag rev. 1. 00 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used withou t the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 46 of 46 10 document revision history revision date description 1.00 october 2 4 , 201 3 first release. sales and further information www.zmdi.com spm@zmdi.com zentrum mikroelektronik dresden ag global headquarters grenzstrasse 28 01109 dresden, germany central office: phone +49.351.8822.0 fax +49.351.8822.600 zmd america, inc. 1525 mccarthy blvd., #212 milpitas, ca 95035 - 7453 usa usa phone +855.275.9634 zentrum mikroelektronik dresden ag, japan o ffice 2nd floor, shinbashi tokyu bldg. 4 - 21 - 3, shinbashi, minato - ku tokyo, 105 - 0004 japan zmd far east, ltd. 3f, no. 51, sec. 2, keelung road 11052 taipei taiwan zentrum mikroelektronik dresden ag, korea office u - space 1 building 11th floor, unit ja - 1102 670 sampyeong - dong bundang - gu, seongnam - si gyeonggi - do, 463 - 400 korea phone +82.31.950.7679 fax +82.504.841.3026 phone +408.883.6310 fax +408.883.6358 phone +81.3.6895.7410 fax +81.3.6895.7301 phone +886.2.2377.8189 fax +886.2.2377.8199 european technical support phone +49.351.8822.7.772 fax +49.351.8822.87.772 disclaimer : this information applies to a product under development. its characteristics and specifications are subject to change witho ut notice. zentrum mikroelek tronik dresden ag (zmd ag ) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. the information furnished hereby is believed to be true and accurate. however, under no circumstances shall zmd ag be liable to a ny customer, licensee, or any other third party for any special, indirect, incidental, or consequential damages of any kind or nature whatsoever arising out of o r in any way related to the furnishing, performance, or use of this technical data. zmd ag hereby expressly disclaims any liabilit y of zmd ag to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liab ility of zmd ag for any damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty, tort (including negligence), strict liability, or otherwise. european sales (stuttgart) phone +49.711.674517.55 fax +49.711.674517.87955

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